ST8024CDR芯片烧写及解密开发

来源: kaiyun平台官网登录 进行技术理解与解密技术实现的分析,方便工程师更好的对解密程序以及芯片本身的特性及应用进行了解,我们提供ST8024CDR芯片的技术资料,供大家做技术参考.
DESCRIPTION
The ST8024 is a complete low cost analog interface for asynchronous 3V and 5V smart cards. It can be placed between the card and the microcontroller with few external components to perform all supply protection and control functions. ST8024 is a direct replacement of ST8004.Main applications are: smartcard readers for Set Top Box, IC card readers for banking, identification, Pay TV.
· IC CARD INTERFACE
· 3 OR 5 V SUPPLY FOR THE IC (VDD AND GND)
· THREE SPECIFICALLY PROTECTED HALF-DUPLEX BI-DIRECTIONAL BUFFERED I/O LINES TO CARD CONTACTS C4, C7 AND C8
· DC/DC CONVERTER FOR VCC GENERATION SEPARATELY POWERED FROM A 5 V ± 20% SUPPLY (VDDP AND PGND)
· 3 OR 5 V ±5% REGULATED CARD SUPPLY VOLTAGE (VCC) WITH APPROPRIATE DECOUPLING HAS THE FOLLOWING
CAPABILITIES:
– ICC < 80 mA at VDDP = 4 to 6.5 V
– HANDLES CURRENT SPIKES OF 40 nAs UP TO 20MHz
– CONTROLS RISE AND FALL TIMES
– FILTERED OVERLOAD DETECTION AT APPROXIMATELY 120 mA
· THERMAL AND SHORT-CIRCUIT PROTECTION ON ALL CARD CONTACTS
· AUTOMATIC ACTIVATION AND DEACTIVATION SEQUENCES; INITIATED BY SOFTWARE OR BY HARDWARE IN THE EVENT OF A SHORT-CIRCUIT, CARD
TAKE-OFF, OVERHEATING, VDD OR VDDP DROP-OUT
· ENHANCED ESD PROTECTION ON CARD SIDE (>6 kV)
· 26 MHz INTEGRATED CRYSTAL OSCILLATOR
· CLOCK GENERATION FOR CARDS UP TO 20 MHz (DIVIDED BY 1, 2, 4 OR 8 THROUGH CLKDIV1 AND CLKDIV2 SIGNALS) WITH SYNCHRONOUS FREQUENCY CHANGES
· NON-INVERTED CONTROL OF RST VIA PIN RSTIN
· ISO 7816, GSM11.11 AND EMV (PAYMENT SYSTEMS) COMPATIBILITY
· SUPPLY SUPERVISOR FOR SPIKE-KILLING DURING POWER-ON AND POWER-OFF AND POWER-ON RESET (THRESHOLD FIXED INTERNALLY OR EXTERNALLY BY A RESISTOR BRIDGE)
· BUILT-IN DEBOUNCE ON CARD PRESENCE CONTACTS
· ONE MULTIPLEXED STATUS SIGNAL OFF
基于ST8024CDR芯片的以上特点,如果您有此 IC解密需求,欢迎来电来访咨询洽谈。